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* other brands and names are the property of their respective owners. information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. july, 2004 copyright ? intel corporation, 2004 order number: 272336-005 8xc52/54/58 chmos single-chip 8-bit microcontroller commercial/express 87c52/80c52/80c32/87c54/80c54/87c58/80c58 * see table 1 for proliferation options y high performance chmos eprom/ rom/cpu y 12/24/33 mhz operations y three 16-bit timer/counters y programmable clock out y up/down timer/counter y three level program lock system y 8k/16k/32k on-chip program memory y 256 bytes of on-chip data ram y improved quick pulse programming algorithm y boolean processor y 32 programmable i/o lines y 6 interrupt sources y programmable serial channel with: e framing error detection e automatic address recognition y ttl and cmos compatible logic levels y 64k external program memory space y 64k external data memory space y mcs 51 microcontroller compatible instruction set y power saving idle and power down modes y once (on-circuit emulation) mode y four-level interrupt priority y extended temperature range except for 33 mhz offering ( b 40 cto a 85 c) memory organization rom eprom romless rom/eprom ram device version version bytes bytes 80c52 87c52 80c32 8k 256 80c54 87c54 80c32 16k 256 80c58 87c58 80c32 32k 256 these devices can address up to 64 kbytes of external program/data memory. the intel 8xc52/8xc54/8xc58 is a single-chip control-oriented microcontroller which is fabricated on intel's reliable chmos iii-e technology. being a member of the mcs 51 family of controllers, the 8xc52/8xc54/ 8xc58 uses the same powerful instruction set, has the same architecture, and is pin-for-pin compatible with the existing mcs 51 family of products. the 8xc52/8xc54/8xc58 is an enhanced version of the 87c51/80c51bh/80c31bh. the added features make it an even more powerful microcontroller for applica- tions that require clock output, and up/down counting capabilities such as motor control. it also has a more versatile serial channel that facilitates multi-processor communications. throughout this document 8xc5x will refer to the 8xc52, 80c32, 8xc54 and 8xc58 unless information applies to a specific device.
8xc52/54/58 table 1. proliferations options standard * 1 -1 -2 -24 -33 80c32 x x x x x 80c52 x x x x x 87c52 x x x x x 80c54 x x x x x 87c54 x x x x x 80c58 x x x x x 87c58 x x x x x notes: * 1 3.5 mhz to 12 mhz; 5v g 20% -1 3.5 mhz to 16 mhz; 5v g 20% -2 0.5 mhz to 12 mhz; 5v g 20% -24 3.5 mhz to 24 mhz; 5v g 20% -33 3.5 mhz to 33 mhz; 5v g 10% 272336 1 figure 1. 8xc5x block diagram 2
8xc52/54/58 proces s information thi s devic e i s manufacture d o n p629.0 , a chmos iii- e process . additiona l proces s an d reliabilit y infor- matio n i s available in the intel ? quality system handbook . packages 40-pi n plasti c di p (otp) 40-pi n cerdi p ( e p r om) 44-pi n plc c (otp) 44-pi n qf p (otp) 27233 6 C 2 dip 27233 6 C 3 plcc 27233 6 C 4 * d o no t connec t reserve d pins. qfp figur e 2 . pi n connections 3
8xc52/54/58 pin descriptions v cc : supply voltage. v ss : circuit ground. v ss1 : secondary ground (not on dip). provided to reduce ground bounce and improve power supply by-passing. note: this pin is not a substitute for the v ss pin (pin 22). (connection not necessary for proper operation.) port 0: port 0 is an 8-bit, open drain, bidirectional i/o port. as an output port each pin can sink several ls ttl inputs. port 0 pins that have 1's written to them float, and in that state can be used as high-im- pedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. in this application it uses strong inter- nal pullups when emitting 1's, and can source and sink several ls ttl inputs. port 0 also receives the code bytes during eprom programming, and outputs the code bytes during program verification. external pullup resistors are re- quired during program verification. port 1: port 1 is an 8-bit bidirectional i/o port with internal pullups. the port 1 output buffers can drive ls ttl inputs. port 1 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current (i il , on the data sheet) because of the internal pull- ups. in addition, port 1 serves the functions of the follow- ing special features of the 8xc5x: port pin alternate function p1.0 t2 (external count input to timer/ counter 2), clock-out p1.1 t2ex (timer/counter 2 capture/ reload trigger and direction control) port 1 receives the low-order address bytes during eprom programming and verifying. port 2: port 2 is an 8-bit bidirectional i/o port with internal pullups. the port 2 output buffers can drive ls ttl inputs. port 2 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. as inputs, port 2 pins that are externally pulled low will source current (i il , on the data sheet) because of the internal pull- ups. port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx @ dptr). in this application it uses strong internal pullups when emitting 1's. dur- ing accesses to external data memory that use 8-bit addresses (movx @ ri), port 2 emits the contents of the p2 special function register. some port 2 pins receive the high-order address bits during eprom programming and program verifica- tion. port 3: port 3 is an 8-bit bidirectional i/o port with internal pullups. the port 3 output buffers can drive ls ttl inputs. port 3 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. as inputs, port 3 pins that are externally pulled low will source current (i il , on the data sheet) because of the pullups. port 3 also serves the functions of various special features of the 8051 family, as listed below: port pin alternate function p3.0 rxd (serial input port) p3.1 txd (serial output port) p3.2 int0 (external interrupt 0) p3.3 int1 (external interrupt 1) p3.4 t0 (timer 0 external input) p3.5 t1 (timer 1 external input) p3.6 wr (external data memory write strobe) p3.7 rd (external data memory read strobe) rst: reset input. a high on this pin for two machine cycles while the oscillator is running resets the de- vice. the port pins will be driven to their reset condi- tion when a minimum v ihi voltage is applied whether the oscillator is running or not. an internal pulldown resistor permits a power-on reset with only a capaci- tor connected to v cc . ale: address latch enable output pulse for latching the low byte of the address during accesses to ex- ternal memory. this pin (ale/prog ) is also the program pulse input during eprom programming for the 87c5x. in normal operation ale is emitted at a constant rate of (/6 the oscillator frequency, and may be used for external timing or clocking purposes. note, how- ever, that one ale pulse is skipped during each ac- cess to external data memory. 4
8xc52/54/58 if desired, ale operation can be disabled by setting bit 0 of sfr location 8eh. with this bit set, the pin is weakly pulled high. however, the ale disable fea- ture will be suspended during a movx or movc in- struction, idle mode, power down mode and ice mode. the ale disable feature will be terminated by reset. when the ale disable feature is suspended or terminated, the ale pin will no longer be pulled up weakly. setting the ale-disable bit has no affect if the microcontroller is in external execution mode. throughout the remainder of this data sheet, ale will refer to the signal coming out of the ale/prog pin, and the pin will be referred to as the ale/prog pin. psen : program store enable is the read strobe to external program memory. when the 8xc5x is executing code from external program memory, psen is activated twice each machine cycle, except that two psen activations are skipped during each access to external data memory. ea /v pp : external access enable. ea must be strapped to vss in order to enable the device to fetch code from external program memory locations 0000h to 0ffffh. note, however, that if any of the lock bits are programmed, ea will be internally latched on reset. ea should be strapped to v cc for internal program executions. this pin also receives the programming supply volt- age (v pp ) during eprom programming. xtal1: input to the inverting oscillator amplifier. xtal2: output from the inverting oscillator amplifi- er. oscillator characteristics xtal1 and xtal2 are the input and output, respec- tively, of a inverting amplifier which can be config- ured for use as an on-chip oscillator, as shown in figure 3. either a quartz crystal or ceramic resonator may be used. more detailed information concerning the use of the on-chip oscillator is available in appli- cation note ap-155, ``oscillators for microcontrol- lers'', order no. 230659. 272336 5 c1, c2 e 30 pf g 10 pf for crystals for ceramic resonators, contact resonator manufac- turer. figure 3. oscillator connections to drive the device from an external clock source, xtal1 should be driven, while xtal2 floats, as shown in figure 4. there are no requirements on the duty cycle of the external clock signal, since the in- put to the internal clocking circuitry is through a di- vide-by-two flip-flop, but minimum and maximum high and low times specified on the data sheet must be observed. an external oscillator may encounter as much as a 100 pf load at xtal1 when it starts up. this is due to interaction between the amplifier and its feedback capacitance. once the external signal meets the v il and v ih specifications the capacitance will not ex- ceed 20 pf. 272336 6 figure 4. external clock drive configuration idle mode the user's software can invoke the idle mode. when the microcontroller is in this mode, power consump- tion is reduced. the special function registers and the onboard ram retain their values during idle, but the processor stops executing instructions. idle mode will be exited if the chip is reset or if an en- abled interrupt occurs. 5
8xc52/54/58 table 2. status of the external pins during idle and power down mode program ale psen port0 port1 port2 port3 memory idle internal 1 1 data data data data idle external 1 1 float data address data power down internal 0 0 data data data data power down external 0 0 float data data data power down mode to save even more power, a power down mode can be invoked by software. in this mode, the oscillator is stopped and the instruction that invoked power down is the last instruction executed. the on-chip ram and special function registers retain their val- ues until the power down mode is terminated. on the 8xc5x either a hardware reset or an external interrupt can cause an exit from power down. reset redefines all the sfrs but does not change the on- chip ram. an external interrupt allows both the sfrs and on-chip ram to retain their values. to properly terminate power down, the reset or ex- ternal interrupt should not be executed before v cc is restored to its normal operating level, and must be held active long enough for the oscillator to restart and stabilize (normally less than 10 ms). with an external interrupt, int0 and int1 must be enabled and configured as level-sensitive. holding the pin low restarts the oscillator but bringing the pin back high completes the exit. once the interrupt is serviced, the next instruction to be executed after reti will be the one following the instruction that put the device into power down. design consideration # the window on the d87c5x must be covered by an opaque label. otherwise, the dc and ac char- acteristics may not be met, and the device may be functionally impaired. # when the idle mode is terminated by a hardware reset, the device normally resumes program exe- cution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. on-chip hardware inhibits access to inter- nal ram in this event, but access to the port pins is not inhibited. to eliminate the possibility of an unexpected write when idle is terminated by re- set, the instruction following the one that invokes idle should not be one that writes to a port pin or to external memory. once mode the once (``on-circuit emulation'') mode facilitates testing and debugging of systems using the 8xc5x without the 8xc5x having to be removed from the circuit. the once mode is invoked by: 1) pull ale low while the device is in reset and psen is high; 2) hold ale low as rst is deactivated. while the device is in once mode, the port 0 pins float and the other port pins and ale and psen are weakly pulled high. the oscillator circuit remains ac- tive. while the 8xc5x is in this mode, an emulator or test cpu can be used to drive the circuit. normal operation is restored when a normal reset is applied. note: for more detailed information on the reduced power modes refer to current embedded microcontrollers and processors handbook volume i, (order no. 270645) and application note ap-252 (embedded applications handbook, order no. 270648), ``designing with the 80c51bh.'' 6
8xc52/54/58 8xc5 x express th e inte l expres s syste m offer s enhancement s to th e operationa l specification s o f th e mc s 5 1 family o f microcontrollers . thes e expres s product s are designe d t o mee t th e need s o f thos e applications whos e operatin g requirement s excee d commercial standards. th e expres s progra m include s th e commercial standar d temperatur e rang e wit h burn-i n an d a n ex- tende d temperatur e rang e wit h o r withou t burn-in. wit h th e commercia l standar d temperatur e range, operationa l characteristic s ar e guarantee d ove r the temperatur e rang e o f 0 c to a 70 c . wit h th e ex- tende d temperatur e rang e option , operationa l char- acteristic s ar e guarantee d ove r th e rang e of - 40 c to + 85 c. th e optiona l burn-i n i s dynami c fo r a minimu m time o f 16 8 hour s a t 125 c wit h v cc = 6.9v 0.25v, followin g guideline s i n mil-std-883 , metho d 1015. fo r th e extende d temperatur e rang e option , this dat a shee t specifie s th e parameter s whic h deviate fro m thei r commercia l temperatur e rang e limits. note: inte l offer s expres s temperatur e specifica- tion s fo r al l 8xc5 x spee d option s excep t for 3 3 mhz. 7
8xc52/54/58 absolute maximum ratings * ambient temperature under bias b 40 cto a 85 c storage temperature b 65 cto a 150 c voltage on ea/v pp pin to v ss 0v to a 13.0v voltage on any other pin to v ss b 0.5v to a 6.5v i ol per i/o pin 15 ma power dissipation1.5w (based on package heat transfer limitations, not device power consumption) notice: this data sheet contains preliminary infor- mation on new products in production. the specifica- tions are subject to change without notice. verify with your local intel sales office that you have the latest data sheet before finalizing a design. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. operating conditions symbol description min max units t a ambient temperature under bias commercial 0 a 70 c express b 40 a 85 c v cc supply voltage 4.0 6.0 v 8xc5x-33 4.5 5.5 v f osc oscillator frequency 8xc5x 3.5 12 mhz 8xc5x-1 3.5 16 mhz 8xc5x-2 0.5 12 mhz 8xc5x-24 3.5 24 mhz 8xc5x-33 3.5 33 mhz dc characteristics (over operating conditions) all parameter values apply to all devices unless otherwise indicated. symbol parameter min typ max unit test conditions (note 4) v il input low voltage b 0.5 0.2 v cc b 0.1 v v il1 input low voltage ea 0 0.2 v cc b 0.3 v v ih input high voltage 0.2 v cc a 0.9 v cc a 0.5 v (except xtal1, rst) v ih1 input high voltage 0.7 v cc v cc a 0.5 v (xtal1, rst) v ol output low voltage (note 5) 0.3 v i ol e 100 m a (note 1) (ports 1, 2 and 3) 0.45 v i ol e 1.6 ma (note 1) 1.0 v i ol e 3.5 ma (note 1) v ol1 output low voltage (note 5) 0.3 v i ol e 200 m a (note 1) (port 0, ale, psen ) 0.45 v i ol e 3.2 ma (note 1) 1.0 v i ol e 7.0 ma (note 1) v oh output high voltage v cc b 0.3 v i oh eb 10 m a (ports 1, 2 and 3, ale, psen ) v cc b 0.7 v i oh eb 30 m a v cc b 1.5 v i oh eb 60 m a 8
8xc52/54/58 dc characteristics (over operating conditions) (continued) all parameter values apply to all devices unless otherwise indicated. symbol parameter min typ max unit test conditions (note 4) v oh1 output high voltage v cc b 0.3 v i oh eb 200 m a (port 0 in external bus mode) v cc b 0.7 v i oh eb 3.2 ma v cc b 1.5 v i oh eb 7.0 ma i il logical 0 input current (ports 1, 2 and 3) b 50 m av in e 0.45v i li input leakage current (port 0) g 10 m av in e v il or v ih i tl logical 1 to 0 transition current (ports 1, 2 and 3) commercial b 650 m av in e 2v express b 750 m a rrst rst pulldown resistor 40 225 k x cio pin capacitance 10 pf @ 1 mhz, 25 c i cc power supply current: (note 3) active mode at 12 mhz (figure 5) 15 30 ma at 16 mhz 20 38 ma at 24 mhz 28 56 ma at 33 mhz (8xc5x-33) 35 56 ma idle mode at 12 mhz (figure 5) 5 7.5 ma at 16 mhz 6 9.5 ma at 24 mhz 7 13.5 ma at 33 mhz (8xc5x-33) 7 15 ma power down mode 5 75 m a 8xc5x-33 5 50 m a notes: 1. capacitive loading on ports 0 and 2 may cause noise pulses above 0.4v to be superimposed on the v ol s of ale and ports 1, 2 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from 1 to 0. in applications where capacitive loading exceeds 100 pf, the noise pulses on these signals may exceed 0.8v. it may be desirable to qualify ale or other signals with a schmitt triggers, or cmos-level input logic. 2. capacitive loading on ports 0 and 2 cause the v oh on ale and psen to drop below the 0.9 v cc specification when the address lines are stabilizing. 3. see figures 6 9 for test conditions. minimum v cc for power down is 2v. 4. typicals are based on a limited number of samples and are not guaranteed. the values listed are at room temperature and 5v. 5. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10ma maximum i ol per 8-bit porte port 0: 26 ma ports 1, 2 and 3: 15 ma maximum total i ol for all output pins: 71 ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 9
8xc52/54/58 272336 7 note: i cc max at 33 mhz is at 5v g 10% v cc , while i cc max at 24 mhz and below is at 5v g 20% v cc figure 5. 8xc52/54/58 i cc vs frequency 272336 8 all other pins disconnected tclch e tchcl e 5ns figure 6. i cc test condition, active mode 10
8xc52/54/58 272336 9 all other pins disconnected tclch e tchcl e 5ns figure 7. i cc test condition idle mode 272336 10 all other pins disconnected figure 8. i cc test condition, power down mode v cc e 2.0v to 6.0v 272336 11 figure 9. clock signal waveform for i cc tests in active and idle modes. tclch e tchcl e 5ns 11
8xc52/54/58 explanation of the ac symbols each timing symbol has 5 characters. the first char- acter is always a `t' (stands for time). the other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. the following is a list of all the characters and what they stand for. a: address c: clock d: input data h: logic level high i: instruction (program memory contents) l: logic level low, or ale p: psen q: output data r: rd signal t: time v: valid w: wr signal x: no longer a valid logic level z: float for example, tavll e time from address valid to ale low tllpl e time from ale low to psen low ac characteristics (over operating conditions, load capacitance for port 0, ale/prog and psen e 100 pf, load capacitance for all other outputs e 80 pf) external memory characteristics all parameter values apply to all devices unless otherwise indicated. in this table, 8xc5x refers to 8xc5x, 8xc5x-1, and 8xc5x-2. symbol parameter oscillator units 12 mhz 24 mhz 33 mhz variable min max min max min max min max 1/tclcl oscillator frequency 8xc5x 3.5 12 mhz 8xc5x-1 3.5 16 mhz 8xc5x-2 0.5 12 mhz 8xc5x-24 3.5 24 mhz 8xc5x-33 3.5 33 mhz tlhll ale pulse width 127 43 21 2 tclcl b 40 ns tavll address valid to ale low 8xc5x 43 tclcl b 40 ns 8xc5x-24 12 tclcl b 30 ns 8xc5x-33 5 tclcl b 25 ns tllax address hold after ale low 8xc5x/-24 53 12 tclcl b 30 ns 8xc5x-33 5 tclcl b 25 ns tlliv ale low to valid instruction in 8xc5x 234 4 tclcl b 100 ns 8xc5x-24 91 4 tclcl b 75 ns 8xc5x-33 56 4 tclcl b 65 ns 12
8xc52/54/58 external memory characteristics (continued) all parameter values apply to all devices unless otherwise indicated. symbol parameter oscillator units 12 mhz 24 mhz 33 mhz variable min max min max min max min max tllpl ale low to psen low 8xc5x/-24 53 12 tclcl b 30 ns 8xc5x-33 5 tclcl b 25 ns tplph psen pulse 205 80 46 3 tclcl b 45 ns width tpliv psen low to valid instruction in 8xc5x 145 3 tclcl b 105 ns 8xc5x-24 35 3 tclcl b 90 ns 8xc5x-33 35 3 tclcl b 55 ns tpxix input 0 0 0 0 ns instruction hold after psen tpxiz input instruction float after psen 8xc5x 59 tclcl b 25 ns 8xc5x-24 21 tclcl b 20 ns 8xc5x-33 5 tclcl b 25 ns taviv address to valid instruction in 8xc5x/-24 312 103 5 tclcl b 105 ns 8xc5x-33 71 5 tclcl b 80 ns tplaz psen low to 10 10 10 10 ns address float trlrh rd pulse 400 150 82 6 tclcl b 100 ns width twlwh wr pulse 400 150 82 6 tclcl b 100 ns width 13
8xc52/54/58 external memory characteristics (continued) all parameter values apply to all devices unless otherwise indicated. symbol parameter oscillator units 12 mhz 24 mhz 33 mhz variable min max min max min max min max trldv rd low to valid data in 8xc5x 252 5 tclcl b 165 ns 8xc5x-24 113 5 tclcl b 95 ns 8xc5x-33 61 5 tclcl b 90 ns trhdx data hold after 0 0 0 0 ns rd trhdz data float after rd 8xc5x/-24 107 23 2 tclcl b 60 ns 8xc5x-33 35 2 tclcl b 25 ns tlldv ale low to valid data in 8xc5x 517 8 tclcl b 150 ns 8xc5x-24/33 243 150 8 tclcl b 90 ns tavdv address to valid data in 8xc5x 585 9 tclcl b 165 ns 8xc5x-24/33 285 180 9 tclcl b 90 ns tllwl ale low to rd 200 300 75 175 41 140 3 tclcl b 50 3 tclcl a 50 ns or wr low tavwl address to rd or wr low 8xc5x 203 4 tclcl b 130 ns 8xc5x-24 77 4 tclcl b 90 ns 8xc5x-33 46 4 tclcl b 75 ns 14
8xc52/54/58 external memory characteristics (continued) all parameter values apply to all devices unless otherwise indicated. symbol parameter oscillator units 12 mhz 24 mhz 33 mhz variable min max min max min max min max tqvwx data valid to wr transition 8xc5x 33 tclcl b 50 ns 8xc5x-24/33 12 0 tclcl b 30 ns twhqx data hold after wr 8xc5x 33 tclcl b 50 ns 8xc5x-24 7 tclcl b 35 ns 8xc5x-33 3 tclcl b 27 ns tqvwh data valid to wr high 8xc5x 433 7 tclcl b 150 ns 8xc5x-24/33 222 142 7 tclcl b 70 ns trlaz rd low to 0 0 0 0 ns address float twhlh rd or wr high to ale high 8xc5x 43 123 tclcl b 40 tclcl a 40 ns 8xc5x-24 12 71 tclcl b 30 tclcl a 30 ns 8xc5x-33 5 55 tclcl b 25 tclcl a 25 ns 15
8xc52/54/58 external program memory read cycle 272336 25 external data memory read cycle 272336 26 external data memory write cycle 272336 27 16
8xc52/54/58 serial port timing - shift register mode test conditions: over operating conditions; load capacitance e 80 pf symbol parameter oscillator units 12 mhz 24 mhz 33 mhz variable min max min max min max min max txlxl serial port 1 0.50 0.36 12 tclcl m s clock cycle time tqvxh output data 700 284 167 10 tclcl b 133 ns setup to clock rising edge txhqx output data hold after clock rising edge 8xc5x 50 2 tclcl b 117 ns 8xc5x-24/33 34 10 2 tclcl b 50 ns txhdx input data hold 0 0 0 0 ns after clock rising edge txhdv clock rising 700 283 167 10 tclcl b 133 ns edge to input data valid shift register mode timing waveforms 272336 15 17
8xc52/54/58 external clock drive symbol parameter min max units 1/tclcl oscillator frequency mhz 8xc5x 3.5 12 mhz 8xc5x-1 3.5 16 mhz 8xc5x-2 0.5 12 mhz 8xc5x-24 3.5 24 mhz 8xc5x-33 3.5 33 mhz tchcx high time 20 ns 8xc5x-24/33 0.35 t osc 0.65 t osc ns tclcx low time 20 ns 8xc5x-24/33 0.35 t osc 0.65 t osc ns tclch rise time 20 ns 8xc5x-24 10 ns 8xc5x-33 5 ns tchcl fall time 20 ns 8xc5x-24 10 ns 8xc5x-33 5 ns external clock drive waveform 272336 16 ac testing input, output waveforms 272336 19 ac inputs during testing are driven at v cc b 0.5v for a logic ``1'' and 0.45v for a logic ``0''. timing measurements are made at v ih min for a logic ``1'' and v il max for a logic ``0''. float waveforms 272336 20 for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs, and begins to float when a 100 mv change from the loaded v oh /v ol level occurs. i ol /i oh e g 20 ma. 18
8xc52/54/58 programming the eprom the part must be running with a 4 mhz to 6 mhz oscillator. the address of an eprom location to be programmed is applied to address lines while the code byte to be programmed in that location is ap- plied to data lines. control and program signals must be held at the levels indicated in table 4. normally ea /v pp is held at logic high until just before ale/ prog is to be pulsed. the ea /v pp is raised to v pp , ale/prog is pulsed low and then ea /v pp is re- turned to a high (also refer to timing diagrams). notes: # exceeding the v pp maximum for any amount of time could damage the device permanently. the v pp source must be well regulated and free of glitches. definition of terms address lines: p1.0 p1.7, p2.0 p2.5 respec- tively for a0 a13. data lines: p0.0 p0.7 for d0 d7. control signals: rst, psen , p2.6, p2.7, p3.3, p3.6, p3.7 program signals: ale/prog ,ea /v pp table 4. eprom programming modes mode rst psen ale/ ea / p2.6 p2.7 p3.3 p3.6 p3.7 prog v pp program code data h l ? 12.75v l h h h h verify code data h l h h l l l h h program encryption h l ? 12.75v l h h l h array address 0 3fh program lock bit 1 h l ? 12.75v h h h h h bits bit 2 h l ? 12.75v h h h l l bit 3 h l ? 12.75v h l h h l read signature byte h l h h l l l l l 19
8xc52/54/58 272336 21 * see table 4 for proper input on these pins figure 10. programming the eprom programming algorithm refer to table 4 and figures 10 and 11 for address, data, and control signals set up. to program the 87c5x the following sequence must be exercised. 1. input the valid address on the address lines. 2. input the appropriate data byte on the data lines. 3. activate the correct combination of control sig- nals. 4. raise ea /v pp from v cc to 12.75v g 0.25v. 5. pulse ale/prog 5 times for the eprom ar- ray, and 25 times for the encryption table and the lock bits. repeat 1 through 5 changing the address and data for the entire array or until the end of the object file is reached. program verify program verify may be done after each byte or block of bytes is programmed. in either case a complete verify of the programmed array will ensure reliable programming of the 87c5x. the lock bits cannot be directly verified. verification of the lock bits is done by observing that their fea- tures are enabled. 272336 22 figure 11. programming signal's waveforms 20
8xc52/54/58 rom and eprom lock system the program lock system, when programmed, pro- tects the onboard program against software piracy. the 80c5x has a one-level program lock system and a 64-byte encryption table. see line 2 of table 5. if program protection is desired. the user submits the encryption table with their code. and both the lock-bit and encryption array are programmed by the factory. the encryption array is not available without the lock bit. for the lock bit to be programmed, the user must submit an encryption table. the 87c5x has a 3-level program lock system and a 64-byte encryption array. since this is an eprom device, all locations are user-programmable. see table 5. encryption array within the eprom array are 64 bytes of encryption array that are initially unprogrammed (all 1's). every time that a byte is addressed during a verify, 6 ad- dress lines are used to select a byte of the encryp- tion array. this byte is then exclusive-nor'ed (xnor) with the code byte, creating an encryption verify byte. the algorithm, with the array in the un- programmed state (all 1's), will return the code in its original, unmodified form. for programming the en- cryption array, refer to table 4 (programming the eprom). when using the encryption array, one important fac- tor needs to be considered. if a code byte has the value 0ffh, verifying the byte will produce the en- cryption byte value. if a large block ( l 64 bytes) of code is left unprogrammed, a verification routine will display the contents of the encryption array. for this reason all unused code bytes should be pro- grammed with some value other than 0ffh, and not all of them the same value. this will ensure maxi- mum program protection. program lock bits the 87c5x has 3 programmable lock bits that when programmed according to table 5 will provide differ- ent levels of protection for the on-chip code and data. erasing the eprom also erases the encryption ar- ray and the program lock bits, returning the part to full functionality. reading the signature bytes the 8xc5x has 3 signature bytes in locations 30h, 31h, and 60h. to read these bytes follow the proce- dure for eprom verify, but activate the control lines provided in table 4 for read signature byte. location device contents 30h all 89h 31h all 58h 60h 80c52 12h 87c52 52h 80c54 14h 87c54 54h 80c58 18h 87c58 58h erasure characteristics (windowed packages only) erasure of the eprom begins to occur when the chip is exposed to light with wavelength shorter than approximately 4,000 angstroms. since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in room- level fluorescent lighting) could cause inadvertent erasure. if an application subjects the device to this type of exposure, it is suggested that an opaque la- bel be placed over the window. the recommended erasure procedure is exposure to ultraviolet light (at 2537 angstroms) to an integrat- ed dose of at least 15 w-sec/cm 2 . exposing the eprom to an ultraviolet lamp of 12,000 m w/cm 2 rating for 30 minutes, at a distance of about 1 inch, should be sufficient. erasure leaves all the eprom cells in a 1's state. 21
8xc52/54/58 table 5. program lock bits and the features program lock bits protection type lb1 lb2 lb3 1 u u u no program lock features enabled. (code verify will still be encrypted by the encryption array if programmed.) 2 p u u movc instructions executed from external program memory are disabled from fetching code bytes from internal memory, ea is sampled and latched on reset, and further programming of the eprom is disabled. 3 p p u same as 2, also verify is disabled. 4 p p p same as 3, also external execution is disabled. note: any other combination of the lock bits is not defined. eprom programming and verification characteristics (t a e 21 cto27 c; v cc e 5v g 20%; v ss e 0v) symbol parameter min max units v pp programming supply voltage 12.5 13.0 v i pp programming supply current 75 ma 1/tclcl oscillator frequency 4 6 mhz tavgl address setup to prog low 48tclcl tghax address hold after prog 48tclcl tdvgl data setup to prog low 48tclcl tghdx data hold after prog 48tclcl tehsh (enable) high to v pp 48tclcl tshgl v pp setup to prog low 10 m s tghsl v pp hold after prog 10 m s tglgh prog width 90 110 m s tavqv address to data valid 48tclcl telqv enable low to data valid 48tclcl tehqz data float after enable 0 48tclcl tghgl prog high to prog low 10 m s 22
8xc52/54/58 e p r o m programmin g an d verificatio n waveforms 27233 6 C 23 * 5 pulse s fo r th e e p r o m array . 2 5 pulse s fo r th e encryptio n tabl e an d loc k bits. therma l impedance al l therma l impedanc e dat a i s approximat e fo r static ai r condition s a t 1 w o f powe r dissipation . value s will chang e dependin g o n operatin g condition s an d ap- plications . se e th e inte l packagin g handboo k (order numbe r 240800 ) fo r a descriptio n o f intel s thermal impedanc e tes t methodology. dat a shee t revisio n history dat a sheet s ar e change d a s ne w devic e information become s available . verif y wit h you r loca l inte l sales offic e tha t yo u hav e th e lates t versio n befor e finaliz- in g a desig n o r orderin g devices. th e followin g difference s exis t betwee n datasheet (272336-00 3 ) an d th e previo u s version (272336-002). 1 . remove d 8xc5x- 3 an d 8xc5x-2 0 fro m th e data sheet. 2 . include d 8xc5x-2 4 an d 8xc5x-3 3 devices. 3 . remove d th e statemen t th e 80c3 2 standard , -1 an d -2 , an d 80c5 2 standard , - 1 an d -2 , d o not hav e th e . . . fro m th e sectio n desig n consid- eration. th e followin g difference s exis t betwee n thi s data- shee t (272336-002 ) an d th e previou s version (272336-001). 1 . remove d 8xc5x- l fro m th e dat a sheet. 2 . include d feature s no t availabl e i n 80c32-stan- dard , - 1 an d -2 , an d 80c52-standard , - 1 an d -2 devices. thi s 8xc5 x datashee t (272336-001 ) replace s the followin g datasheets: 87c52/80c52/80c3 2 270757-003 87c52/80c52/80c3 2 expres s 270868-002 87c52-20/80c52-20/80c32-2 0 272272-001 87c54/80c5 4 270816-004 87c54/80c5 4 expres s 270901-001 87c54-20/- 3 80c54-20/- 3 270941-003 87c54/80c5 8 270900-003 87c58/80c5 8 expres s 270902-001 87c58-20/- 3 80c58-20/- 3 272029-002 23 th e followin g difference s exis t betwee n thi s data- shee t (272336-00 5 ) an d th e previo u s version (272336-00 4/-003). 1 . remove d references to package prefixes. when possible, prefix variables replaced with x .

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